1. Technical Field
The present invention relates to a memory module and, more particularly, to a memory module having memory devices and a method of testing the same.
2. Discussion of the Related Art
A typical memory system includes a memory control circuit and a plurality of memory modules. Each of the plurality of memory modules includes a plurality of semiconductor memory devices. The plurality of semiconductor memory devices are connected to a plurality of data lines, which in turn connect to the memory control circuit.
As operating speeds of typical memory systems increase, a memory module has been proposed, which includes a buffer device for transmitting data between the memory control circuit and the plurality of memory modules at high speeds.
FIG. 1 is a block diagram illustrating a conventional memory system including such a buffer device. The memory system of FIG. 1 includes a memory module 100 and a memory control circuit 200. The memory module 100 includes dynamic random access memories (DRAMs) 20-1–20-8 and a buffer device 10. An operation of the memory system of FIG. 1 will be discussed below.
The memory control circuit 200 transmits differential serial data to the buffer device 10 and receives differential serial data transmitted from the buffer device 10. The buffer device 10 multiplexes the differential serial data transmitted from the memory control circuit 200, converts the differential serial data into single parallel data, and transmits the single parallel data to the DRAMs 20-1–20-8 during a write operation. The buffer device 10 also demultiplexes the single parallel data received from the DRAMs 20-1–20-8, converts the single parallel data into differential serial data, and transmits the differential serial data to the memory control circuit 200 during a read operation. Each of the DRAMs 20-1–20-8 stores the single parallel data transmitted from the buffer device 10 during a write operation and outputs the single parallel data to the buffer device 10 during a read operation.
Differential serial data is data associated with a predetermined bit of parallel data that was serially input to the buffer device 10, and bits of the differential serial data are in pairs having “high” levels and “low” levels. Single parallel data is a predetermined bit of parallel data and bits of the single parallel data have either a “high” level or a “low” level. The differential serial data is smaller in bit number than the single parallel data.
FIG. 2 is a block diagram illustrating the buffer device 10 of the conventional memory system of FIG. 1. The buffer device 10 includes a multiplexer 11, demultiplexer 12, differential input buffer 15, differential output buffer 16, input buffer 13 and output buffer 14. An operation of the buffer device 10 will be discussed below.
The multiplexer 11 converts n-bits of differential serial data into parallel to generate m-bits of single parallel data. For example, when “n” is 16 and “m” is 8, the multiplexer 11 serially receives differential serial data of 2-bits four times to generate single parallel data having 8-bits. In other words, 2-bit differential serial data is serially input four times to the multiplexer 11 and converted into single parallel data having 8-bits.
The demultiplexer 12 converts m-bits of single parallel data into serial to generate n-bits of differential serial data. For example, when “n” is 16 and “m” is 8, the demultiplexer 12 converts single parallel data having 8-bits into 2-bit serial data, which is then serially output four times. In other words, 8-bit single parallel data is serially converted into 2-bit data that is serially output four times.
The differential input buffer 15 buffers n-bits of differential serial data output from the memory control circuit 200 and outputs buffered differential serial data to the multiplexer 11. The differential output buffer 16 buffers n-bits of differential serial data output from the demultiplexer 12 and outputs the buffered differential serial data to the memory control circuit 200.
The input buffer 13 buffers data having 8 m-bits output from the multiplexer 11 and transmits the buffered data to corresponding DRAMs 20-1–20-8. The output buffer 14 buffers data having 8 m-bits output from corresponding DRAMs 20-1–20-8 and transmits the buffered data to the demultiplexer 12.
As described above, the conventional memory system serially transmits 2-bit data between the memory control circuit 200 and the buffer device 10 and transmits differential serial data in order to reduce a common mode noise during data transmission. Here, a data rate between the buffer device 10 and the DRAMs 20-1–20-8 is higher than a data rate between the memory control circuit 200 and the buffer device 10 when transmitting data at high speed. Thus, as data is serially transmitted between the memory control circuit 200 and the buffer device 10, the number of data lines is reduced, and a data rate is increased to transmit data at high speed.
However, in the conventional memory system it is difficult to test the semiconductor memory devices of the memory module to see if they are operating properly. This occurs, because when the frequency of a clock signal applied by a tester is lower than the frequency of a clock signal used by the memory control circuit, it is difficult to perform a test, and it is difficult to apply a test pattern to the buffer device.